Pipelined Asynchronous Circuits

Lines, Andrew Matthew (1998) Pipelined Asynchronous Circuits. Technical Report. California Institute of Technology. [CaltechCSTR:1998.cs-tr-95-21]

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Abstract

This thesis presents a design style for implementing communicating sequential processes (CSP) as quasi delay insensitive asynchronous circuits, based on the compilation method of [1]. Although hand compilation can always yield optimal circuits to a good designer, a restricted approach is suggested which can easily implement circuits with some slack between inputs and outputs. These circuits are fast and versatile building blocks for highly pipelined designs. The first chapter presents the implementation approach for individual cells. The second chapter investigates the time behavior of complex pipelined circuits, with the goal of adding slack where necessary and adjusting transistor sizes to optimize the overall throughput.

EPrint Type:	Monograph (Technical Report)
Subjects:	All Records
ID Code:	184
Deposited By:	Caltech Library System
Deposited On:	30 April 2001
Record Number:	CaltechCSTR:1998.cs-tr-95-21
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:1998.cs-tr-95-21
Usage Policy:	You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.

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