Low-Energy Asynchronous Memory Design

Tierno, Jose A. and Martin, Alain J. (1994) Low-Energy Asynchronous Memory Design. Technical Report. California Institute of Technology. [CaltechCSTR:1994.cs-tr-94-21]

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Abstract

We introduce the concept of energy per operation as a measure of performance of an asynchronous circuit. We show how to model energy consumption based on the high-level language specification. This model is independent of voltage and timing considerations. We apply this model to memory design. We show first how to dimension a memory array, and how to break up this memory array into smaller arrays to minimize the energy per access. We then show how to use cache memory and pre-fetch mechanisms to further reduce energy per access.

EPrint Type:	Monograph (Technical Report)
Subjects:	All Records
ID Code:	231
Deposited By:	Caltech Library System
Deposited On:	14 May 2001
Record Number:	CaltechCSTR:1994.cs-tr-94-21
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:1994.cs-tr-94-21
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