A Theory of Constant Et^2 CMOS Circuits

Papadantonakis, Karl (2001) A Theory of Constant Et^2 CMOS Circuits. Technical Report. California Institute of Technology. [CaltechCSTR:2001.004]

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Abstract

CMOS pulldown networks are characterized by their switching energy (E) and propagation delay (t), and voltage scaling has been shown to allow E or t to be adjusted, while Et^2 remains constant. Previously, this argument about single pulldown stages was applied to arbitrary digital circuits by assuming that the total delay of any such circuit was a sum of single pulldown and pullup stage delays, neglecting the time variation of the input to each stage. In this paper, the statement that Et^2 is independent of voltage scaling is generalized to arbitrary networks of CMOS transitors using only a weaker assumption: that every node has a capacitance.

EPrint Type:	Monograph (Technical Report)
Additional Information:	Caltech Asynchronous VLSI Group
Uncontrolled Keywords:	energy efficiency Et^2 CMOS circuits VLSI voltage scaling delay ODE
Subjects:	All Records
ID Code:	286
Deposited By:	Karl Papadantonakis
Deposited On:	27 September 2001
Record Number:	CaltechCSTR:2001.004
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:2001.004
Usage Policy:	You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.

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