The Torus Routing Chip

Dally, William J. and Seitz, Charles L. (1986) The Torus Routing Chip. Technical Report. California Institute of Technology. [CaltechCSTR:1986.5208-tr-86]

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Abstract

The torus routing chip (TRC) is a self-timed chip that performs deadlock-free cut-through routing in k-ary n-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels. A prototype TRC with byte wide self-timed communication channels achieved on first silicon a throughput of 64Mbits/s in each dimension, about an order of magnitude better performance than the communication networks used by machines such as the Caltech Cosmic Cube or Intel iPSC. The latency of the cut-through routing of only 150ns per routing step largely eliminates message locality considerations in the concurrent programs for such machines. The design and testing of the TRC as a self-timed chip was no more difficult than it would have been for a synchronous chip.

EPrint Type:	Monograph (Technical Report)
Subjects:	All Records
ID Code:	297
Deposited By:	Caltech Library System
Deposited On:	03 December 2001
Record Number:	CaltechCSTR:1986.5208-tr-86
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:1986.5208-tr-86
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