Pipelined Asynchronous Cache Design

Nystroem, Mika (1997) Pipelined Asynchronous Cache Design. Technical Report. California Institute of Technology. [CaltechCSTR:2001.009]

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Abstract

This thesis describes the development of pipelined asynchronous cache memories. The work is done in the context of the performance characteristics of memories and transistor logic of a late 1990's high-performance asynchronous microprocessor. We describe the general framework of asynchronous memory systems, caching, and those system characteristics that make caching of growing importance and keep it an interesting research topic. Finally, we prese nt the main contribution of this work, which is a latency-tolerating asynchronous cache micro-architecture suitable for asynchronous microprocessors. In Chapter~Two, we present a case study of the Level~1 data and instruction caches for the Caltech MiniMIPS asynchronous microprocessor, currently under development at Caltech. The implementation is quasi-delay-insensitive in 0.6~micron scalable CMOS rules, with a logic latency of approximately 2~nanoseconds.

EPrint Type:	Monograph (Technical Report)
Uncontrolled Keywords:	asynchronous vlsi qdi quasi delay-insensitive CMOS pipelined cache design low-power
Subjects:	All Records
ID Code:	310
Deposited By:	Mika Nystroem
Deposited On:	12 December 2001
Record Number:	CaltechCSTR:2001.009
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:2001.009
Usage Policy:	You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.

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