Transistor Sizing of Energy-Delay--Efficient Circuits

Penzes, Paul and Nystroem, Mika and Martin, Alain (2002) Transistor Sizing of Energy-Delay--Efficient Circuits. Technical Report. California Institute of Technology. [CaltechCSTR:2002.003]

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Abstract

This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, i.e., for optimal Et^n where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that reflects the chosen trade-off between energy and delay. We propose a set of analytical formulas that closely approximate the optimal transistor sizes. We then study an efficient iteration procedure that can further improve the original analytical solution. Based on these results, we introduce a novel transistor sizing algorithm for energy-delay efficiency.

EPrint Type:	Monograph (Technical Report)
Uncontrolled Keywords:	transistor sizing
Subjects:	All Records
ID Code:	318
Deposited By:	Paul Penzes
Deposited On:	11 April 2002
Record Number:	CaltechCSTR:2002.003
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:2002.003
Usage Policy:	You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.

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