Speed and Energy Performance of an Asynchronous MIPS R3000 Microprocessor

Martin, Alain J. and Nystroem, Mika and Penzes, Paul and Wong, Catherine (2001) Speed and Energy Performance of an Asynchronous MIPS R3000 Microprocessor. Technical Report. California Institute of Technology. [CaltechCSTR:2001.012]

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Abstract

This paper presents the speed and energy figures for an asynchronous implementation of a MIPS R3000 microprocessor. The design is almost entirely QDI and introduces a new fine-grained pipeline. The performance figures show that this design is four times as efficient as equivalent clocked designs and that its cycle time in FO4 units compares to that of high-performance dynamic pipelines.

EPrint Type:	Monograph (Technical Report)
Uncontrolled Keywords:	asynchronous VLSI, MIPS microprocessor, quasi delay-insensitive, energy-efficient, test results, asynchronous microprocessor
Subjects:	All Records
ID Code:	451
Deposited By:	Catherine Wong
Deposited On:	25 September 2002
Record Number:	CaltechCSTR:2001.012
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:2001.012
Usage Policy:	You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.

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