An Asynchronous Register Bypass Transformation

Papadantonakis, Karl (2003) An Asynchronous Register Bypass Transformation. Technical Report. California Institute of Technology. [CaltechCSTR:2003.005]

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Abstract

A register specification typically states that in each cycle there is a possible read followed by a possible write; the sequence is strict. A register core with a separate read and write port is more efficient, because it can read and write to different locations simultaneously, and hence in one cycle. In the Caltech MiniMIPS processor, a control structure was added to such a register core, so that it implements the desired specification.

EPrint Type:	Monograph (Technical Report)
Uncontrolled Keywords:	Register Bypass Asynchronous VLSI Program Transformation
Subjects:	All Records
ID Code:	495
Deposited By:	Karl Papadantonakis
Deposited On:	25 June 2003
Record Number:	CaltechCSTR:2003.005
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:2003.005
Usage Policy:	You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.

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