An Architecture for Asynchronous FPGAs

Wong, Catherine G. and Martin, Alain J. and Thomas, Peter (2003) An Architecture for Asynchronous FPGAs. Technical Report. IEEE Computer Society Press. [CaltechCSTR:2003.006a]

This is the latest version of this eprint.

Full text available as:

Postscript - Requires a viewer, such as GhostView

Abstract

We present an architecture for a quasi delay-insensitive asynchronous field-programmable gate array. The logic cell is a complete asynchronous pipeline stage and the interconnects are entirely delay insensitive, eliminating all timing issues from the place-and-route procedure.

EPrint Type:	Monograph (Technical Report)
Uncontrolled Keywords:	FPGA, reconfigurable, asynchronous, delay-insensitive
Subjects:	All Records
ID Code:	516
Deposited By:	Catherine Wong
Deposited On:	05 November 2003
Record Number:	CaltechCSTR:2003.006a
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:2003.006a
Usage Policy:	You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.

Available Versions of this Item

An Architecture for Asynchronous FPGAs (deposited 25 August 2003)
- An Architecture for Asynchronous FPGAs (deposited 05 November 2003) [Currently Displayed]

Archive Staff Only: edit this record