The torus: an exercise in constructing a processing surface

Martin, Alain J. (1982) The torus: an exercise in constructing a processing surface. Technical Report. California Institute of Technology, Pasadena, CA. [CaltechCSTR:1982.5047-tr-82]

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Abstract

A "Processing Surface" is defined as a large, dense, and regular arrangement of processor and storage modules on a two-dimensional surface, e.g. a VLSI chip. A general method is described for distributing parallel recursive computations over such a surface. Scope rules enforcing the "locality" of variables and procedure parameters are introduced in the programming language. These rules and a particular interconnection of the modules on the surface make it possible to transmit parameter and variable values between modules without using extraneous communication actions. The choice of the Processing Surface topology for binary recursive computations is discussed and a torus-like topology is chosen.

EPrint Type:	Monograph (Technical Report)
Additional Information:	Proceedings of the Second Caltech Conference on VLSI, January 1981
Subjects:	All Records
ID Code:	576
Deposited By:	Kristin Buxton
Deposited On:	21 May 2008
Record Number:	CaltechCSTR:1982.5047-tr-82
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:1982.5047-tr-82
Usage Policy:	You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.

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