Hierarchical power routing

Johannsen, Dave (1978) Hierarchical power routing. Technical Report. California Institute of Technology, Pasadena, CA. [CaltechCSTR:1978.2069-tr-78]

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Abstract

Advances in LSI technology allow the system designer to implement large amounts of processing capability on a single silicon chip. It will soon be possible to construct a large number of processing elements on these chips. How will the system designer organize these processing elements? Hierarchically designed array or tree machines arc two possible alternatives. This paper provides a background for study of array and tree machines by examining how to supply power to an array of processing elements.

EPrint Type:	Monograph (Technical Report)
Subjects:	All Records
ID Code:	592
Deposited By:	Kristin Buxton
Deposited On:	18 July 2008
Record Number:	CaltechCSTR:1978.2069-tr-78
Official Persistent URL:	http://resolver.caltech.edu/CaltechCSTR:1978.2069-tr-78
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